While integrated circuit power supply levels continue to fall to smaller levels, it remains desirable to accommodate input signals for integrated circuits that have voltage levels higher than a low power supply level. As but one particular example, low voltage transistor-transistor logic (LVTTL) signals can swing from between about 0 to 3.3 volts. However, integrated circuits may be capable of operating internally at much lower voltage levels (e.g., 1.2 volts). Thus, in order to provide compatibility with LVTTL systems, an integrated circuit can include a voltage translator, or level shift circuit that can translate a higher voltage signal (e.g., LVTTL 0-3.3 volts) to a lower voltage signal (e.g., 0-1.2 volts).
A conventional input circuit for accommodating level shifting is set forth in FIG. 6 and designated by the general reference character 600. An input circuit 600 can include two stages: a high voltage stage 602 and a low voltage stage 604. A high voltage stage 604 can provide a differential comparison between a high voltage input signal VINHV and a reference voltage to thereby provide a high voltage input signal VIN′. For example, the logic of an input signal VINHV that varies between about 0 and 3.3 volts can be compared to a reference voltage of about 1.5 volts. A resulting output signal VIN′ from high voltage stage 602 can be a high voltage signal (e.g., swing between about 0 and 3.3 volts) having a level dependent upon the differential comparison between the high voltage input signal VINHV and the reference voltage.
In order to accommodate lower voltage internal circuits of a semiconductor device (e.g., complementary metal-oxide-semiconductor (CMOS) voltage levels), a high voltage signal VIN′ can be translated to lower voltage levels by a low voltage stage 604. A low voltage stage 604 can level shift signal VIN′ from a high voltage (e.g., 0 to 3.3 volts) to a low voltage (e.g., 0 to 1.2 volts). Thus, a resulting output signal VINLV from low voltage stage 604 can be a low voltage signal.
As illustrated in FIG. 6, a conventional input circuit 600 can receive two different power supplies. In particular, a high voltage stage 602 can receive a high voltage supply (e.g., 3.3/2.5 volts) while a low voltage stage 604 can receive a low voltage supply (1.2 volts). Thus, high voltage stage 602 may include high voltage devices, such as transistors and the like, capable of receiving high voltage levels, while a low voltage stage 604 may include low voltage devices, which may not be optimized for the higher voltage levels.
More particularly, a high voltage stage 602 can include high voltage insulated gate field effect transistors (IGFETs) having a thicker gate insulator and/or different source/drain doping. Still further, higher voltage devices are typically placed in different diffusion regions (e.g., wells) than lower voltage devices and/or can have larger spacing requirements than lower voltage devices.
A more detailed example of a conventional input circuit, like that set forth in FIG. 6, is shown in a schematic diagram in FIG. 7. The input circuit of FIG. 7 is designated by the general reference character 700, and can include a high voltage stage 702 and a low voltage stage 704. A high voltage stage 702 can include a bias current circuit 706, a differential pair 708, and an active load circuit 710. A current bias circuit 706 can be connected to a high voltage power supply, VDD, and supply a bias current to differential pair 708. Differential pair 708 can draw a differential current based on a comparison between input signals VINHV and VREF. An active load circuit 710 can provide a high voltage output signal VIN′ based on the differential current of the differential pair 708.
It is noted that all of the transistors of the bias current circuit 706 and differential pair 708 are high voltage transistors, indicated by the label MAX. Thus, such transistors can occupy more space than low voltage transistors. Further, high voltage p-channel transistors in CMOS circuits can be particularly undesirable, as such transistors are typically twice as large as corresponding high voltage n-channel transistors. Further, the high voltage stage 702 is connected to a high power supply voltage VDD.
It is further noted that some, or all of the n-channel transistors within a high voltage stage 702 may also be high voltage transistors.
Thus, in the conventional arrangement, signal amplification is performed in a high voltage domain with a high supply voltage VDD and high voltage transistors.
A conventional low voltage stage 704 can include voltage limiting section 712 and an inverter 714. Voltage limiting section 712 can generate an output signal based on high voltage signal VIN′. The majority of the transistors of the low voltage stage 704 can be low voltage transistors that operate at a power supply voltage VPW that is lower than VDD.
A conventional input circuit 700 can introduce a signal delay of about 700 picoseconds (ps). This delay can result from delay introduced by the differential compare operation of high voltage stage 702, as well as the level shifting operation provided by low voltage stage 704.
While the conventional input circuits described above can translate a high voltage signal to a low voltage signal, it is always desirable to arrive at some way of improving the performance of such circuits.
For example, it is almost always desirable to arrive at an input circuit having a faster operating speed and/or lower power consumption than a conventional approach. It is noted that high swing nodes of the conventional input circuit 700 (e.g., drains of differential compare transistors in differential pair 708), as well as “crowbar” current in the level shifting section 712, can result in undesirably high power consumption.
In addition, because circuit size can relate proportionally to cost, it is desirable to arrive at some way of reducing circuit size.
Still further, it is desirable to reduce the complexity of circuit design. For example, as shown in FIG. 8, because the above described conventional circuit has two power supply voltages (VDD and VPW), an integrated circuit employing such a circuit must include a low power supply routing 814 and a high power supply routing 812. In addition, as noted above, a dual power supply device typically has separate regions for high and low voltage devices. For example, high voltage devices may reside in one region 810, while low voltage devices may reside in a different region 808. As but one very detailed example, region 810 can include high voltage p-channel devices formed in n-wells biased to a high voltage VDD, while region 808 can include p-channel devices formed in n-wells biased to the lower voltage VPW. In an even more particular example, a low voltage region 808 of conventional integrated circuit 800 may include logic circuits 804 and core circuits 806. Core circuits 806 can include memory cells and the like.
Along these same lines, a dual voltage device (e.g., one operating at VDD and VPW) may suffer from concerns related to power sequencing (i.e., the order, rate, etc., at which such different power supplies are applied to the device). That is, a multiple power supply device may have additional latch-up susceptibility and/or complexity in establishing logic states. Further, power sequencing typically demands a particular order, which simply adds to the complexity of start-up operations for an electronic device that contains the integrated circuit.
In addition, in the conventional example of FIG. 7, current sources (I1, I2 and I3) are provided to establish biasing currents for a differential pair and active current mirror load. The current source bias values can be I1=5 micro amps (μA), I2=5 μA, and I3=15 μA. Typically, such circuits are based on “band-gap” reference voltage circuits (band-gap circuits), and thus present a load on the band-gap circuits. It would be desirable to arrive at some way of reducing band-gap circuit load, as such reductions can reduce overall circuit size and complexity. For example, conventional band-gap circuits typically include a bipolar transistor structure, or the like, having an area proportional to current load. By reducing band gap current load, size and power of the device can reduced.